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LT3741 High Power, Constant Current, Constant Voltage, Step-Down Controller FeaTures
n n n n n n n n n n
DescripTion
The LT(R)3741 is a fixed frequency synchronous step-down DC/DC controller designed to accurately regulate the output current at up to 20A. The average current-mode controller will maintain inductor current regulation over a wide output voltage range of 0V to (VIN - 2V). The regulated current is set by an analog voltage on the CTRL pins and an external sense resistor. Due to its unique topology, the LT3741 is capable of sourcing and sinking current. The regulated voltage and overvoltage protection are set with a voltage divider from the output to the FB pin. Soft-Start is provided to allow a gradual increase in the regulated current during startup. The switching frequency is programmable from 200kHz to 1MHz through an external resistor on the RT pin or through the use of the SYNC pin and an external clock signal. Additional Features include an accurate external reference voltage for use with the CTRL pins, an accurate UVLO/EN pin that allows for programmable UVLO hysteresis, and thermal shutdown.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7199560, 7321203 and others pending.
Control Pin Provides Accurate Control of Regulated Output Current 1.5% Voltage Regulation Accuracy 6% Current Regulation Accuracy 6V to 36V Input Voltage Range Wide Output Voltage Range Up to (VIN - 2V) Average Current Mode Control <1A Shutdown Current Up to 94% Efficiency Additional Pin for Thermal Control of Load Current Thermally Enhanced 4mm x 4mm QFN and 20-Pin FE Package
applicaTions
n n n
n
General Purpose Industrial Super-Cap Charging Applications Needing Extreme Short-Circuit Protection and/or Accurate Output Current Limit Constant Current or Constant Voltage Source
Typical applicaTion
10V/20A Constant Current, Constant Voltage Step-Down Converter
EN/UVLO 82.5k EN/UVLO RT SYNC LT3741 10nF VREF CTRL1 VC RHOT 45.3k 39.2k 5.6nF CTRL2 RNTC SS VCC_INT 22F LG GND SENSE+ SENSE- FB 12.1k
3741 TA01a
VIN 1F HG 220nF 2.2H 2.5m 100F
VIN 14V TO 36V
VOUT vs IOUT
12 10 VOUT 10V 20A 8 VOUT (V) 6 4 2 VIN = 18V VOUT = 10V ILIMIT = 20A 0 0246
CBOOT SW
150F 2 88.7k
10nF
8 10 12 14 16 18 20 22 IOUT (A)
3741 TA01b
3741f
LT3741 absoluTe maximum raTings (Note 1)
VIN Voltage ................................................................40V EN/UVLO Voltage ........................................................6V VREF Voltage................................................................3V CTRL1 and CTRL2 Voltage ..........................................3V SENSE+ Voltage ........................................................40V SENSE- Voltage ........................................................40V VC Voltage ..................................................................3V SW Voltage ...............................................................40V CBOOT ......................................................................46V CBOOT - SW Voltage ..................................................6V RT Voltage...................................................................3V FB Voltage ...................................................................3V SS Voltage ..................................................................6V VCC_INT Voltage ...........................................................6V SYNC Voltage ..............................................................6V Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) TSSOP .............................................................. 300C
pin conFiguraTion
TOP VIEW VCC_INT CBOOT TOP VIEW SW VCC_INT GND 15 HG 21 GND 14 GND 13 SYNC 12 RT 11 GND 6 SS 7 FB 8 SENSE+ 9 10 SENSE- VC VIN EN/UVLO VREF CTRL2 GND CTRL1 SS 1 2 3 4 5 6 7 8 9 21 GND 20 LG 19 CBOOT 18 SW 17 HG 16 GND 15 SYNC 14 RT 13 VC 12 SENSE- 11 SENSE+ VIN EN/UVLO 1 VREF 2 CTRL2 3 GND 4 CTRL1 5 LG
20 19 18 17 16
FB 10
UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 38C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
orDer inFormaTion
LEAD FREE FINISH LT3741EUF#PBF LT3741IUF#PBF LT3741EFE#PBF LT3741IFE#PBF TAPE AND REEL LT3741EUF#TRPBF LT3741IUF#TRPBF LT3741EFE#TRPBF LT3741IFE#TRPBF PART MARKING* 3741 3741 LT3741FE LT3741FE PACKAGE DESCRIPTION 20-Lead (4mm x 4mm) Plastic QFN 20-Lead (4mm x 4mm) Plastic QFN 20-Lead Plastic TSSOP 20-Lead Plastic TSSOP TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3741f
LT3741 elecTrical characTerisTics
PARAMETER Input Voltage Range VIN Pin Quiescent Current (Note 2) Non-Switching Operation Shutdown Mode EN/UVLO Pin Falling Threshold EN/UVLO Hysteresis EN/UVLO Pin Current SYNC Pin Threshold CTRL1 Pin Control Range CTRL1 Pin Current Reference Reference Voltage (VREF Pin) Inductor Current Sensing Full Range SENSE+ to SENSE- SENSE+ Pin Current SENSE- Pin Current Internal VCC Regulator (VCC_INT Pin) Regulation Voltage NMOS FET Driver Non-Overlap time HG to LG Non-Overlap time LG to HG Minimum On-Time LG Minimum On-Time HG Minimum Off-Time LG High Side Driver Switch On-Resistance Gate Pull Up Gate Pull Down Low Side Driver Switch On-Resistance Gate Pull Up Gate Pull Down Switching Frequency fSW Soft-Start Charging Current Voltage Regulation Amplifier Input Bias Current gm Feedback Regulation Voltage CTRL1 = 1.5V, ISENSE- = 23A
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
CONDITIONS
l
MIN 6
TYP
MAX 36
UNITS V mA A V mV A V
Not Switching VEN/UVLO = 0V
l
1.8 0.1 1.49 1.55 130 5.5 1.0 0
2.5 1 1.61
VIN = 6V, EN/UVLO = 1.45V
1.5 100
V nA
CTRL1 = 1.5V 1.94 48
2 51 50 10
2.06 54
V mV nA A
VCTRL1 = 1.5V With VOUT ~ 4V, VCTRL1 = 0V
l
4.7
5 100 60
5.2
V ns ns ns ns ns
(Note 3) (Note 3) (Note 3) VCBOOT - VSW = 5V VCC_INT = 5V
50 80 65 2.3 1.3 2.3 1.0
l
RT = 40k RT = 200k
900 190
1000 218 11
1070 233
kHz kHz A nA A/V
FB = 1.3V 1.192
850 800 1.21 1.228
V
3741f
LT3741 elecTrical characTerisTics
PARAMETER Current Control Loop gm Amp Offset Voltage Input Common Mode Range VCM(LOW) VCM(HIGH) Output Impedance gm Differential Gain Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3741E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C 375
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VEN/UVLO = 5V, unless otherwise noted.
CONDITIONS MIN -3 TYP 0 0 2 3.5 475 1.7 625 MAX 3 UNITS mV V V M A/V mV/V
VCM(HIGH) Measured from VIN to VCM
to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3741I is guaranteed to meet performance specifications over the -40C to 125C operating junction temperature range. Note 3: The minimum on and off times are guaranteed by design and are not tested.
3741f
LT3741 Typical perFormance characTerisTics
EN/UVLO Threshold (Falling)
1.70 10
EN/UVLO Pin Current
0.5
IQ in Shutdown
EN/UVLO PIN CURRENT (A)
EN/UVLO THRESHOLD (V)
1.64
8
0.4
-50C 1.52 1.46 130C
IQ (A)
1.58
6
0.3 130C
4 2
0.2 0.1
1.40
6
12
18
24 VIN (V)
30
36
3741 G01
0
25C 130C -50C 6 12 18 24 VIN (V) 30 36
3741 G02
25C 0 0 8 16 24 VIN (V) 32 40
3741 G03
Quiescent Current (Non-Switching)
2.0 2.06 2.05 QUIESCENT CURRENT (mA) 1.6 VREF VOLTAGE (V) 2.04 2.03 2.02 2.01 2.00 1.99 36
3741 G04
VREF Pin Voltage
1.6
VREF Current Limit
VIN = 36V ILIMIT (mA) VIN = 6V
1.4
TA = 25C TA = 130C
1.2
1.2
0.8 0.4
TA = -50C 1.0
0
TA = 25C TA = 130C TA = -50C 6 12 18 24 VIN (V) 30
1.98 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G05
0.8
6
12
18
24 VIN (V)
30
36
3741 G06
RT Pin Current Limit
90 14 13 80 12 11 ISS (A) 10 9 8 7 40 -50 -15 55 20 TEMPERATURE (C) 90 125
3741 G08
Soft-Start Pin Current
6 5 VIN = 36V VIN = 6V VCC_INT (V) 90 125
3741 G09
VCC_INT Current Limit
ILIMIT (A)
70
4 3 2 1 0
60 50
6 -50
VIN = 12V TA = 25C 0 10 20 30 40 ILOAD (mA) 50 60
3741 G07
-15
55 20 TEMPERATURE (C)
3741f
LT3741 Typical perFormance characTerisTics
Internal UVLO
5.0 3.00 2.75 4.5 VOLTAGE (V) 2.50 2.25 2.00 1.75 3.0 -50 1.50 -50 UVLO (V) 3.50 3.25 3.00 2.75 2.50 -50
CBOOT-SW UVLO Voltage
4.00 3.75
VCC_INT UVLO
VIN (V)
4.0
3.5
-15
55 20 TEMPERATURE (C)
90
125
3741 G10
-15
20 55 TEMPERATURE (C)
90
125
3741 G11
-15
20 55 TEMPERATURE (C)
90
125
3741 G12
VCC_INT Load Reg at 12V
6.0 150 100 CONTROL CURRENT (%) 50 0 -50 -100 -150 0 10 20 30 40 ILOAD (mA) 50 60
3741 G13
Regulated Current vs VFB
1.75 OVERVOLTAGE THRESHOLD (V)
Overvoltage Threshold
5.6
1.65
VCC_INT (V)
5.2 25C 4.8 4.4
1.55
1.45
-50C 130C 1.15 1.20 1.25 VFB (V) 1.30 1.35
3741 G14
1.35
4.0
-200 1.10
1.25 -50
-25
0 25 75 50 TEMPERATURE (C)
100
125
3741 G15
Overvoltage Timeout
19 60 50 VSENSE+ - VSENSE- (mV)
Regulated Sense Voltage
2.5
Common Mode Lockout
MEASURED VIN - VOUT VIN = 6V VIN = 36V
OVERVOLTAGE TIMEOUT (s)
17
2.0 CM LOCKOUT (V)
15
40 30 20 10 0
1.5
13 11
1.0 0.5
9 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G16
0
0.5
1.0 VCTRL (V)
1.5
2.0
3741 G17
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G18
3741f
LT3741 Typical perFormance characTerisTics
HG Driver RDS(ON)
5 5
LG Driver RDS(ON)
300
Minimum Off-Time
RDS(ON) ( )
RDS(ON) ( )
3
PULL-UP
3 PULL-UP 2 1 PULL-DOWN
MINIMUM OFF-TIME (ns)
4
4
240
HG
180
2 PULL-DOWN 1
120 LG 60
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G20
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G21
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G25
Non-Overlap Time
150 150
Minimum On-Time
1.5
Oscillator Frequency
1.2MHz
NON-OVERLAP TIME (ns)
120
MINIMUM ON-TIME (ns)
HG TO LG
120 FREQUENCY (MHz)
1.2 900kHz
90 LG TO HG
90 HG 60 LG 30
0.9
60 30
0.6 0.3
220kHz
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G23
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G24
0 -50
-15
55 20 TEMPERATURE (C)
90
125
3741 G36
Overcurrent Threshold
120 100 VSENSE+ - VSENSE- (mV) 80 60 40 20 0 3 2
Current Regulation Accuracy CTRL1 = 1.5V, VIN = 12V
6 4 2 0 -2 -4 -6
Current Regulation Accuracy CTRL1 = 0.75V, VIN = 12V
ACCURACY (%)
0 25C -1 -2 -3
ACCURACY (%)
1
25C
0
0.75
1.5 CTRL_H (V)
2.25
3.0
3741 G28
0
2.5 5.0 7.5 OUTPUT VOLTAGE (V)
10
3741 G26
0
2.5 5.0 7.5 OUTPUT VOLTAGE (V)
10
3741 G27
3741f
LT3741 Typical perFormance characTerisTics
VOUT vs IOUT
6 5 4 VOUT (V) 3 2 1 VIN = 20V VOUT = 5V ILIMIT = 24A 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IOUT (A)
3741 G19
VOUT vs IOUT
25
20
VOUT (V)
15
10
5 V = 25V IN VOUT = 20V ILIMIT = 9.5A 0 0123
4
56 IOUT (A)
7
8
9
10
3741 G22
VOUT vs IOUT
12 10 EFFICIENCY (%) 8 VOUT (V) 6 4 2 VIN = 24V VOUT = 10V ILIMIT = 18A 0 0246 100 95 90 85 80
Efficiency and Power Loss vs Load Current
30 25 20 15 10 POWER LOSS 75 70 VIN = 20V VOUT = 5V 0 5 10 15 LOAD CURRENT (A) 20 25
3741 G29
EFFICIENCY
POWER LOSS (W)
5 0
8
10 12 14 16 18 20 IOUT (A)
3741 G33
Efficiency and Power Loss vs Load Current
100 95 EFFICIENCY (%) 90 85 80 75 70 EFFICIENCY 4.8 4.0 EFFICIENCY (%) 3.2 2.4 1.6 0.8 0 POWER LOSS (W) 100 95 90 85 80 75 70 65 60 55 50 45 40
Efficiency and Power Loss vs Load Current
12 EFFICIENCY 10 8 6 4 2 0 POWER LOSS (W)
POWER LOSS
POWER LOSS VIN = 25V VOUT = 20V 0 2 4 6 LOAD CURRENT (A) 8 10
3741 G30
VIN = 24V VOUT = 10V 0 5 10 15 LOAD CURRENT (A) 20
3741 G37
3741f
LT3741 Typical perFormance characTerisTics
5A Load Step Recovery
VOUT 20mV/DIV AC-COUPLED
Voltage Regulation with 10A Regulated Inductor Current
VOUT 2V/DIV
IL 2A/DIV
IL 5A/DIV
COUT = 470F
20ms/DIV
3741 G31
100s/DIV
3741 G34
Common Mode Lockout
EN/UVLO 5V/DIV VOUT 2V/DIV IL 5A/DIV
Shutdown and Recovery 1.5nF Soft-Start Capacitor
IL 200mA/DIV
VOUT 2V/DIV 1ms/DIV
3741 G35
VIN = 7V
100s/DIV COUT = 1mF VOUT = 5V 10A LOAD 18A CURRENT LIMIT
3741 G32
3741f
LT3741 pin FuncTions
(QFN/TSSOP)
EN/UVLO (Pin 1/Pin 4): Enable Pin. The EN/UVLO pin acts as an enable pin and turns on the internal current bias core and subregulators at 1.55V. The pin does not have any pull-up or pull-down, requiring a voltage bias for normal part operation. Full shutdown occurs at approximately 0.5V. VREF (Pin 2/Pin 5): Buffered 2V reference capable of 0.5mA drive. CTRL2 (Pin 3/Pin 6): Thermal control input used to reduce the regulated current level. GND (Pins 4,11,14, Exposed Pad Pin 21/Pins 2,7,16, Exposed Pad Pin 21): Ground. The exposed pad must be soldered to the PCB CTRL1 (Pin 5/Pin 8): The CTRL1 pin sets the high level regulated output current and overcurrent. The maximum input voltage is internally clamped to 1.5V. The overcurrent set point is equal to the high level regulated current level set by the CTRL1 pin with an additional 23mV offset between the SENSE+ and SENSE- pins. SS (Pin 6/Pin 9): The Soft-Start Pin. Place an external capacitor to ground to limit the regulated current during start-up conditions. The soft-start pin has a 11A charging current. This pin controls regulated output current determined by CTRL1. FB (Pin 7/Pin 10): Feedback Pin for Voltage Regulation and Overvoltage Protection. The feedback voltage is 1.21V. Overvoltage is also sensed through the FB pin. When the feedback voltage exceeds 1.5V, the overvoltage lockout prevents switching for 13s to allow the inductor current to discharge. SENSE+ (Pin 8/Pin 11): SENSE+ is the inverting input of the average current mode loop error amplifier. This pin is connected to the external current sense resistor, RS. The voltage drop between SENSE+ and SENSE- referenced to the voltage drop across an internal resistor produces the input voltages to the current regulation loop. of the average current mode loop error amplifier. The reference current, based on CTRL1 or CTRL2 flows out of the pin to the output side of the sense resistor, RS. SENSE- (Pin 9/Pin 12): SENSE- is the non-inverting input
VC (Pin 10/Pin 13): VC provides the necessary compensation for the average current loop stability. Typical compensation values are 20k to 50k for the resistor and 2nF to 5nF for the capacitor. RT (Pin 12/Pin 14): A resistor to ground sets the switching frequency between 200kHz and 1MHz. When using the SYNC function, set the frequency to be 20% lower than the SYNC pulse frequency. This pin is current limited to 60A. Do not leave this pin open. SYNC (Pin 13/Pin 15): Frequency Synchronization Pin. This pin allows the switching frequency to be synchronized to an external clock. The RT resistor should be chosen to operate the internal clock at 20% slower than the SYNC pulse frequency. This pin should be grounded when not in use. When laying out board, avoid noise coupling to or from SYNC trace. HG (Pin 15/Pin 17): HG is the top-FET gate drive signal that controls the state of the high-side external power FET. The driver impedance is approximately 1.8. SW (Pin 16/Pin 18): The SW pin is used internally as the lower-rail for the floating high-side driver. Externally, this node connects the two power-FETs and the inductor. CBOOT (Pin 17/Pin 19): The CBOOT pin provides a floating 5V regulated supply for the high-side FET driver. An external Schottky diode is required from the VCC_INT pin to the CBOOT pin to charge the CBOOT capacitor when the switch-pin is near ground. LG (Pin 18/Pin 20): LG is the bottom-FET gate drive signal that controls the state of the low-side external power-FET. The driver impedance is approximately 1.8. VCC_INT (Pin 19/Pin 1): A regulated 5V output for charging the CBOOT capacitor. VCC_INT also provides the power for the digital and switching subcircuits. Below 6V VIN, tie this pin to the rail. VCC_INT is current limited to 50mA. Shutdown operation disables the output voltage drive. VIN (Pin 20/Pin 3): Input Supply Pin. Must be locally bypassed with a 4.7F low-ESR capacitor to ground.
3741f
0
LT3741 block Diagram
VIN 402k 1 133k 2 VREF 2V REFERENCE EN/UVLO INTERNAL REGULATOR AND UVLO VCC_INT 19
(QFN Package)
VIN 20 VIN
1F
47F
10F
100nF
12 82.5k
RT
OSCILLATOR
CURRENT MIRROR 11A
5
CTRL1
gm AMP gm = 450A/V RO = 4M IOUT = 40A
CTRL BUFFER 90k
100nF
3 10 40.2k 5.6F
CTRL2 VC
VOLTAGE REGULATOR AMP gm = 850A/V
Figure 1. Block Diagram
+
6
SS 1.21V
-
+
1.5V
-
+
-
R PWM COMPARATOR S Q
SYNC
13
SYNC
HIGH SIDE CBOOT DRIVER 17 HG 15 SW SYNCRONOUS 16 CONTROLLER LG 18 LOW SIDE DRIVER SENSE+
0.1F
2.4H
8 RS 5m 9 VOUT 150F 2
3k
SENSE-
+ + -
FB
40.2k 7 10k
3741 F01
3741f
LT3741 operaTion
The LT3741 utilizes fixed-frequency, average current mode control to accurately regulate the inductor current, independently from the output voltage. This is an ideal solution for applications requiring a regulated current source. The control loop will regulate the current in the inductor at an accuracy of 6%. Once the output has reached the regulation voltage determined by the resistor divider from the output to the FB pin and ground, the inductor current will be reduced by the voltage regulation loop. In voltage regulation, the output voltage has an accuracy of 1.5%. For additional operation information, refer to the Block Diagram in Figure 1. The current control loop has two reference inputs, determined by the voltage at the analog control pins, CTRL1 and CTRL2. The lower of the two analog voltages on CTRL1 and CTRL2 determines the regulated output current. The analog voltage at the CTRL1 pin is buffered and produces a reference voltage across an internal resistor. The internal buffer has a 1.5V clamp on the output, limiting the analog control range of the CTRL1 and CTRL2 pins from 0V to 1.5V - corresponding to a 0mV to 51mV range on the sense resistor, RS. The average current-mode control loop uses the internal reference voltage to regulate the inductor current, as a voltage drop across the external sense resistor, RS. A 2V reference voltage is provided on the VREF pin to allow the use of a resistor voltage divider to the CTRL1 and CTRL2 pins. The VREF pin can supply up to 500A and is current limited to 1mA. The error amplifier for the average current-mode control loop has a common mode lockout that regulates the inductor current so that the error amplifier is never operated out of the common mode range. The common mode range is from 0V to 2V below the VIN supply rail. The overcurrent set point is equal to the regulated current level set by the CTRL1 pin with an additional 23mV offset between the SENSE+ and SENSE- pins. The overcurrent is limited on a cycle-by-cycle basis; shutting switching down once the overcurrent level is reached. Overcurrent is not soft-started. The regulated output voltage is set with a resistor divider from the output back to the FB pin. The reference at the FB pin is 1.21V. If the output voltage level is high enough to engage the voltage loop, the regulated inductor current will be reduced to support the load at the output. If the voltage at the FB pin reaches 1.5V (~25% higher than the regulation level), an internal overvoltage flag is set, shutting down switching for 13s. The EN/UVLO pin functions as a precision shutdown pin. When the voltage at the EN/UVLO pin is lower than 1.55V, the internal reset flag is asserted and switching is terminated. Full shutdown occurs at approximately 0.5V with a quiescent current of less than 1A in full shutdown. The EN/UVLO pin has 130mV of built-in hysteresis. In addition, a 5.5A current source is connected to this pin that allows any amount of hysteresis to be added with a series resistor or resistor divider from VIN. During startup, the SS pin is held low until the internal reset goes low. Once reset goes low, the capacitor at the soft-start pin is charged with an 11A current source. The internal buffers for the CTRL1 and CTRL2 signals are limited by the voltage at the soft-start pin, slowly ramping the regulated inductor current to the current determined by the voltage at the CTRL1 or CTRL2 pins. The thermal shutdown is set at 163C with 8C hysteresis. During thermal shutdown, all switching is terminated and the part is in reset (forcing the SS pin low). The switching frequency is determined by a resistor at the RT pin. The RT pin is also limited to 60A, while not recommended, this limits the switching frequency to 2MHz when the RT pin is shorted to ground. The LT3741 may also be synchronized to an external clock through the use of the SYNC pin.
3741f
LT3741 applicaTions inFormaTion
Programming Inductor Current The analog voltage at the CTRL1 pin is buffered and produces a reference voltage, VCTRL, across an internal resistor. The regulated average inductor current is determined by: IO = VCTRL1 30 * RS Inductor Selection Size the inductor to have no less than 30% peak-to-peak ripple. The overcurrent set point is equal to the high level regulated current level set by the CTRL1 pin with an additional 23mV offset between the SENSE+ and SENSE- pins. The saturation current for the inductor should be at least 20% higher than the maximum regulated current. The following equation sizes the inductor for best performance: V *V -V 2 L = IN O O 0.3 * fS * IO * VIN where VO is the output voltage, IO is the maximum regulated current in the inductor and fS is the switching frequency. Using this equation, the inductor will have approximately 15% ripple at maximum regulated current.
Table 2. Recommended Inductor Manufacturers
VENDOR Coilcraft Sumida Vishay POWER DISSIPATION (W) 0.05 0.25 0.5 1.25
POWER DISSIPATION (W) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 10 5 0 0 0 6 14 16 18 20
3741 F03
where RS is the external sense resistor and IO is the average inductor current, which is equal to the output current. Figure 2 shows the maximum output current vs RS. The maximum power dissipation in the resistor will be: PRS
(0.05V )2 =
RS
Table 1 contains several resistors values, the corresponding maximum current and power dissipation in the sense resistor. Susumu, Panasonic and Vishay offer accurate sense resistors. Figure 3 shows the power dissipation in RS.
Table 1. Sense Resistor Values
MAXIMUM OUTPUT CURRENT (A) RESISTOR, RS (m) 1 5 10 25
30 MAXIMUM OUTPUT CURRENT (A) 25 20 15
WEBSITE www.coilcraft.com www.sumida.com www.vishay.com www.we-online.com www.nec-tokin.com
Wurth Electronics NEC-Tokin
50 10 5 2
2
4
8 10 12 RS (m )
0
2
4
6
8 10 12 14 16 18 20 RS (m )
3741 F02
Figure 3. Power Dissipation in RS
Figure 2. RS Value Selection for Regulated Output Current
3741f
LT3741 applicaTions inFormaTion
Switching MOSFET Selection When selecting switching MOSFETs, the following parameters are critical in determining the best devices for a given application: total gate charge (QG), on-resistance (RDS(ON)), gate to drain charge (QGD), gate-to-source charge (QGS), gate resistance (RG), breakdown voltages (maximum VGS and VDS) and drain current (maximum ID). The following guidelines provide information to make the selection process easier. Both of the switching MOSFETs need to have their maximum rated drain currents greater than the maximum inductor current. The following equation calculates the peak inductor current: V *V -V 2 IMAX = IO + IN O O 2 * fS * L * VIN where VIN is the input voltage, L is the inductance value, VO is the output voltage, IO is the regulated output current and fS is the switching frequency. During MOSFET selection, notice that the maximum drain current is temperature dependant. Most data sheets include a table or graph of the maximum rated drain current vs temperature. The maximum VDS should be selected to be higher than the maximum input supply voltage (including transient) for both MOSFETs. The signals driving the gates of the switching MOSFETs have a maximum voltage of 5V with respect to the source. During start-up and recovery conditions, the gate drive signals may be as low as 3V. To ensure that the LT3741 recovers properly, the maximum threshold should be less than 2V. For a robust design, select the maximum VGS greater than 7V. Power losses in the switching MOSFETs are related to the on-resistance, RDS(ON); the transitional loss related to the gate resistance, RG; gate-to-drain capacitance, QGD and gate-to-source capacitance, QGS. Power loss to the on-resistance is an Ohmic loss, I2 RDS(ON), and usually dominates for input voltages less than ~15V. Power losses to the gate capacitance dominate for voltages greater than ~12V. When operating at higher input voltages, efficiency can be optimized by selecting a high side MOSFET with higher RDS(ON) and lower CGD. The power loss in the high side MOSFET can be approximated by: PLOSS = (ohmic loss) + (transition loss)
(V +R I ) PLOSS F D O * IO2 RDS(ON) * T + VIN VIN * IOUT 5V * (QGD + QGS ) * ( 2 * RG + RPU + RPD ) * fS
(
)
where T is a temperature-dependant term of the MOSFET's on-resistance. Using 70C as the maximum ambient operating temperature, T is roughly equal to 1.3. RPD and RPU are the LT3741 high side gate driver output impedance, 1.3 and 2.3 respectively. A good approach to MOSFET sizing is to select a high side MOSFET, then select the low side MOSFET. The tradeoff between RDS(ON), QG, QGD and QGS for the high side MOSFET is shown in the following example. VO is equal to 4V. Comparing two N-channel MOSFETs, with a rated VDS of 40V and in the same package, but with 8x different RDS(ON) and 4.5x different QG and QGD: , M1: RDS(ON) = 2.3m, QG = 45.5nF , QGS = 13.8nF QGD = 14.4nF , RG = 1 , M2: RDS(ON) = 18m, QG = 10nF , QGS = 4.5nF QGD = 3.1nF , RG = 3.5 Power loss for both MOSFETs is shown in Figure 4. Observe that while the RDS(ON) of M1 is eight times lower, the power loss at low input voltages is equal, but four times higher at high input voltages than the power loss for M2. Another power loss related to switching MOSFET selection is the power lost to driving the gates. The total gate charge, QG, must be charged and discharged each switching cycle. The power is lost to the internal LDO within the LT3741. The power lost to the charging of the gates is: PLOSS_LDO (VIN - 5V) * (QGLG + QGHG) * fS where QGLG is the low side gate charge and QGHG is the high side gate charge. Whenever possible, utilize a switching MOSFET that minimizes the total gate charge to limit the internal power dissipation of the LT3741.
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LT3741 applicaTions inFormaTion
7 6 MOSFET POWER LOSS (W) 5 4 3 2 1 0 0 10 20 INPUT VOLTAGE (V)
3741 F04a
2.5 2.0
TOTAL TRANSITIONAL
MOSFET POWER LOSS (W)
1.5 1.0
TOTAL
TRANSITIONAL OHMIC
0.5
OHMIC 30 40 0 0 10 20 INPUT VOLTAGE (V)
3741 F04b
30
40
Figure 4a. Power Loss Example for M1 Figure 4 Table 3. Recommended Switching FETs
VIN VOUT IOUT (V) (V) (A) 8 24 24 12 36 24 4 4 2-4 2-4 4 4 TOP FET BOTTOM FET MANUFACTURER
Figure 4b. Power Loss Example for M2
5-10 RJK0365DPA RJK0330DPB Renesas 5 RJK0368DPA RJK0332DPB www.renesas.com 20 10 20 40 RJK0365DPA FDMS8680 Si7884BDP PSMN4R030YL RJK0346DPA FDMS8672AS Fairchild www.fairchildsemi.com SiR470DP Vishay www.vishay.com
The capacitors also need to be surge rated to the maximum output current. To achieve the lowest possible ESR, several low ESR capacitors should be used in parallel. Many applications benefit from the use of high density POSCAP capacitors, which are easily destroyed when exposed to overvoltage conditions. To prevent this, select POSCAP capacitors that have a voltage rating that is at least 50% higher than the regulated voltage CBOOT Capacitor Selection The CBOOT capacitor must be sized less than 220nF and more than 50nF to ensure proper operation of the LT3741. Use 220nF for high current switching MOSFETs with high gate charge. VCC_INT Capacitor Selection The bypass capacitor for the VCC_INT pin should be larger than 5F for stability and has no ESR requirement. It is recommended that the ESR be lower than 50m to reduce noise within the LT3741. For driving MOSFETs with gate charges larger than 10nC, use 0.5F/nC of total gate charge. Soft-Start Unlike conventional voltage regulators, the LT3741 utilizes the soft-start function to control the regulated inductor current. The charging current is 11A and reduces the regulated current when the SS pin voltage is lower than CTRL1.
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RJK0346DPA NXP/Philips www.nxp.com
Input Capacitor Selection The input capacitor should be sized at 4F for every 1A of output current and placed very close to the high side MOSFET. A small 1F ceramic capacitor should be placed near the VIN and ground pins of the LT3741 for optimal noise immunity. The input capacitor should have a ripple current rating equal to half of the maximum output current. It is recommended that several low ESR ceramic capacitors be used as the input capacitance. Use only type X5R or X7R capacitors as they maintain their capacitance over a wide range of operating voltages and temperatures. Output Capacitor Selection The output capacitors need to have very low ESR (equivalent series resistance) to reduce output ripple. A minimum of 20F/A of load current should be used in most designs.
LT3741 applicaTions inFormaTion
Output Current Regulation To adjust the regulated load current, an analog voltage is applied to the CTRL1 pin. Figure 5 shows the regulated voltage across the sense resistor for control voltages up to 2V. Figure 6 shows the CTRL1 voltage created by a voltage divider from VREF to ground. When sizing the resistor divider, please be aware that the VREF pin is current limited to 500A. Above 1.5V, the control voltage has no effect on the regulated inductor current.
60 50 VSENSE+ - VSENSE- (mV) 40 30 20 10 0 VREF LT3741 CTRL1 R1
3741 F06
R2
Figure 6. Analog Control of Inductor Current
VOUT LT3741 FB R1
3741 F07
R2
Figure 7. Output Voltage Regulation and Overvoltage Protection Feedback Connections
0
0.5
1.0 VCTRL (V)
1.5
2.0
3741 F05
not leave this pin open under any condition. The RT pin is also current limited to 60A. See Table 4 and Figure 8 for resistor values and the corresponding switching frequencies.
Table 4. Switching Frequency
SWITCHING FREQUENCY (MHz) 1 0.750 0.5 0.3 0.2 0.1
1.2 1.0 FREQUENCY (MHz) 0.8 0.6 0.4 0.2 0
Figure 5. Sense Voltage vs CTRL Voltage
RT (k) 40.2 53.6 82.5 143 221 453
Voltage Regulation and Overvoltage Protection The LT3741 uses the FB pin to regulate the output voltage and to provide a high speed overvoltage lockout to avoid high voltage conditions. The regulated output voltage is programmed using a resistor divider from the output and ground (Figure 7). When the output voltage exceeds 125% of the regulated voltage level (1.5V at the FB pin), the internal overvoltage flag is set, terminating switching. The regulated output voltage must be greater than 1.5V and is set by the equation: R2 VOUT = 1.21V 1+ R1 Programming Switching Frequency The LT3741 has an operational switching frequency range between 200kHz and 1MHz. This frequency is programmed with an external resistor from the RT pin to ground. Do
0
50 100 150 200 250 300 350 400 450 500 RT (k )
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Figure 8. Frequency vs RT Resistance
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LT3741 applicaTions inFormaTion
Thermal Shutdown The internal thermal shutdown within the LT3741 engages at 163C and terminates switching and resets soft-start. When the part has cooled to 155C, the internal reset is cleared and soft-start is allowed to charge. Switching Frequency Synchronization The nominal switching frequency of the LT3741 is determined by the resistor from the RT pin to ground and may be set from 200kHz to 1MHz. The internal oscillator may also be synchronized to an external clock through the SYNC pin. The external clock applied to the SYNC pin must have a logic low below 0.3V and a logic high higher than 1.25V. The input frequency must be 20% higher than the frequency determined by the resistor at the RT pin. The duty cycle of the input signal needs to be greater than 10% and less than 90%. Input signals outside of these specified parameters will cause erratic switching behavior and subharmonic oscillations. When synchronizing to an external clock, please be aware that there will be a fixed delay from the input clock edge to the edge of switch. The SYNC pin must be grounded if the synchronization to an external clock is not required. When SYNC is grounded, the switching frequency is determined by the resistor at the RT pin. Shutdown and UVLO The LT3741 has an internal UVLO that terminates switching, resets all synchronous logic, and discharges the soft-start capacitor for input voltages below 4.2V. The LT3741 also has a precision shutdown at 1.55V on the EN/UVLO pin. Partial shutdown occurs at 1.55V and full shutdown is guaranteed below 0.5V with <1A IQ in the full shutdown state. Below 1.55V, an internal current source provides 5.5A of pull-down current to allow for programmable UVLO hysteresis. The following equations determine the voltage divider resistors for programming the UVLO voltage and hysteresis as configured in Figure 9. R2 = VHYST 5.5A
LT3741 EN/UVLO R1
3741 F09
VIN R2
VIN
Figure 9. UVLO Configuration
The EN/UVLO pin has an absolute maximum voltage of 6V. To accommodate the largest range of applications, there is an internal Zener diode that clamps this pin. For applications where the supply range is greater than 4:1, size R2 greater than 375k. Load Current Derating Using the CTRL2 Pin The LT3741 is designed specifically for driving high power loads. In high current applications, derating the maximum current based on operating temperature prevents damage to the load. In addition, many applications have thermal limitations that will require the regulated current to be reduced based on load and/or board temperature. To achieve this, the LT3741 uses the CTRL2 pin to reduce the effective regulated current in the load. While CTRL1 programs the regulated current in the load, CTRL2 can be configured to reduce this regulated current based on the analog voltage at the CTRL2 pin. The load/board temperature derating is programmed using a resistor divider with a temperature dependant resistance (Figure 10). When the board/load temperature rises, the CTRL2 voltage will decrease. To reduce the regulated current, the CTRL2 voltage must be lower than voltage at the CTRL1 pin.
RV VREF R2 LT3741 CTRL2 R1 (OPTION A TO D) A B C D RNTC RNTC RX RNTC RNTC RX
3741 F10
RV
Figure 10. Load Current Derating vs Temperature Using NTC Resistor
1.55V * R2 R1= VUVLO - 1.55V
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LT3741 applicaTions inFormaTion
Average Current Mode Control Compensation The use of average current mode control allows for precise regulation of the inductor and load currents. Figure 11 shows the average current mode control loop used in the LT3741, where the regulation current is programmed by a current source and a 3k resistor.
VCTRL * 11A/V 3k RS
the error amplifier will be the compensation resistor, RC. Use the following equation as a good starting point for compensation component sizing: RC = fS * L * 1000 V 0.002 [], CC = [F ] VO * RS fS
MODULATOR
L
gm ERROR AMP RC CC
+
LOAD
where fS is the switching frequency, L is the inductance value, VO is the output voltage and RS is the sense resistor. For most applications, a 4.7nF compensation capacitor is adequate and provides excellent phase margin with optimized bandwidth. Please refer to Table 6 for recommended compensation values. Board Layout Considerations
-
3741 F11
Figure 11. LT3741 Average Current Mode Control Scheme
To design the compensation network, the maximum compensation resistor needs to be calculated. In current mode controllers, the ratio of the sensed inductor current ramp to the slope compensation ramp determines the stability of the current regulation loop above 50% duty cycle. In the same way, average current mode controllers require the slope of the error voltage to not exceed the PWM ramp slope during the switch off-time. Since the closed-loop gain at the switching frequency produces the error signal slope, the output impedance of
Table 6. Recommended Compensation Values
VIN (V) 12 12 12 24 24 VO (V) 4 4 5 4 4 IL (A) 5 10 20 2 20 fSW (MHz) 0.5 0.5 0.25 0.5 0.5
Average current mode control is relatively immune to the switching noise associated with other types of control schemes. Placing the sense resistor as close as possible to the SENSE+ and SENSE- pins avoids noise issues. Due to sense resistor ESL (equivalent series inductance), a 10 resistor in series with the SENSE+ and SENSE- pins with a 33nF capacitor placed between the SENSE pins is recommended. Utilizing a good ground plane underneath the switching components will minimize interplane noise coupling. To dissipate the heat from the switching components, use a large area for the switching mode while keeping in mind that this negatively affects the radiated noise.
L (H) 1.5 1.5 1.8 1.0 1.0
RS (m) 5 5 2.5 2.5 2.5
RC (k) 47.5 47.5 38.3 52.3 52.3
CC (nF) 4.7 4.7 8.2 4.7 4.7
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LT3741 Typical applicaTions
20A Super Capacitor Charger with 5V Regulated Output
EN/UVLO EN/UVLO VIN 1F RT SYNC VREF HG CBOOT 2.2F SW LT3741 VCC_INT LG GND CTRL2 RNTC 470k 10nF SS VC SENSE+ SENSE- FB 47.5k 4.7nF 33nF 38.3k 12.1k L1: IHLP4040DZER1R0M01 M1: RJK0365DPA M2: RJK0346DPA R1: VISHAY WSL25122L500FEA
3741 TA02
100F M1 L1 1.0H R1 2.5m
VIN 10V TO 36V
82.5k
100nF
VOUT 20A MAXIMUM 150F 2
RHOT 45.3k
22F
10 M2
10
50k
CTRL1
Efficiency and Power Loss vs Load Current
100 95 EFFICIENCY (%) 90 85 80 POWER LOSS 75 70 VIN = 20V VOUT = 5V 0 5 10 15 LOAD CURRENT (A) 20 25
3741 TA02b
VOUT vs IOUT
30 25 20 15 10 5 0 POWER LOSS (W) 6 5 4 VOUT (V) 3 2 1 VIN = 20V VOUT = 5V ILIMIT = 20A 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IOUT (A)
3741 TA02c
EFFICIENCY
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LT3741 Typical applicaTions
20A LED Driver
EN/UVLO EN/UVLO VIN 1F RT SYNC VREF HG CBOOT 2.2F RHOT CONTROL INPUT 45.3k SW LT3741 VCC_INT LG GND CTRL2 RNTC 470k 10nF SS SENSE
+
100F M1 L1 1.1H 2.5m
VIN 12V TO 36V
82.5k
150nF
VOUT 6V, 20A MAXIMUM D1 680F
22F
CTRL1
M2 10 10
SENSE- VCH 82.5k 4.7nF FB
33nF 47.5k 12.1k
3741 TA03
LED Current Waveforms 10A to 20A Current Step
CTRL1 1V/DIV 1.5V 0.75V 20A ILED 5A/DIV 10A
1ms/DIV
3741 TA03b
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0
LT3741 Typical applicaTions
10A Single-Cell Lithium-Ion Battery Charger
EN/UVLO CONTROLLER CTRL1 RT SYNC VREF 2.2F RHOT 45.3k CTRL2 RNTC 470k 1nF SS VC HG CBOOT LT3741 SW VIN 1F 220nF 2.2H 33F VIN 24V
82.5k
1% 5m
VOUT 4.2V, 10A MAXIMUM
+
3.6V 22F 10 10
VCC_INT LG GND SENSE+ SENSE- FB 82.5k 8.2nF 20nF
30.1k 12.1k
3741 TA04
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LT3741 package DescripTion
(Reference LTC DWG # 05-08-1710 Rev A)
UF Package 20-Lead Plastic QFN (4mm x 4mm)
0.70 0.05 4.50 0.05 3.10 0.05 2.00 REF 2.45 0.05 2.45 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 PIN 1 TOP MARK (NOTE 6) 2.00 REF 2.45 0.10 0.75 0.05 R = 0.05 TYP BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER
19 20 0.40 0.10 1 2
4.00 0.10
2.45 0.10
(UF20) QFN 01-07 REV A
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
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LT3741 package DescripTion
FE Package 20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
3.86 (.152) 6.40 - 6.60* (.252 - .260) 3.86 (.152) 20 1918 17 16 15 14 13 12 11
6.60 0.10 4.50 0.10
SEE NOTE 4
2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC
6.40 2.74 (.252) (.108) BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 1.20 (.047) MAX
0 - 8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE20 (CB) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT3741 Typical applicaTion
20V Regulated Output with 5A Current Limit
EN/UVLO EN/UVLO VIN 1F RT SYNC VREF HG CBOOT 2.2F SW LT3741 VCC_INT LG GND CTRL2 RNTC 470k 10nF SS VC SENSE+ SENSE- FB 30.1k 3.9nF 10nF 187k 12.1k
3741 TA05
22F M1 L1 8.2H R1 10m
VIN 36V
82.5k
100nF
VOUT 5A MAXIMUM 100F
RHOT 45.3k
22F
10 M2
10
CTRL1
relaTeD parTs
PART NUMBER LT3743 DESCRIPTION Synchronous Step-Down LED Driver COMMENTS 92% Efficiency, IOUT to 20A, VIN: 5.5V to 36V, IQ = 2mA, ISD < 1A, 4mm x 5mm QFN-28, TSSOP-28E
3741f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
LT 0310 * PRINTED IN USA
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010

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